HI5767EVAL2【PDF 1/16 页】EVALUATION PLATFORM HI5767

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录983

[1页]2页 3页 4页 5页

HI5767EVAL2 Evaluation Board User’s Manual

Description

Application Note

January 1999

AN9762

The HI5767EVAL2 evaluation board allows the circuit

designer to evaluate the performance of the Intersil HI5767

monolithic 10-bit 20/40/60MSPS analog-to-digital converter

(ADC). As shown in the Evaluation Board Functional Block

Diagram, the evaluation board includes sample clock

generation circuitry, a single-ended to differential analog

input RF transformer configuration, an on board external

variable reference voltage generator and a digital data

output header/connector. The digital data outputs are

conveniently provided for easy interfacing to a ribbon

connector or logic probes. In addition, the evaluation board

includes some prototyping area for the addition of user

designed custom interfaces or circuits.

The sample clock generator circuit accepts the external

sampling signal through an SMA type RF connector, J2.

This input is AC-coupled and terminated in 50 ? allowing for

connection to most laboratory signal generators. In

addition, the duty cycle of the clock driving the A/D

Evaluation Board Functional Block Diagram

converter is adjustable by way of a potentiometer. This

allows the effects of sample clock duty cycle on the HI5767

to be observed.

The analog input signal is also connected through an SMA

type RF connector, J1, and applied to a single-ended to

differential analog input RF transformer. This input is

AC-coupled and terminated in 50 ? allowing for connection

to most laboratory signal generators.

The converters’ digital data outputs along with two phases of

the sample clock (CLK and CLK) are provided at the output

header/connector. With this output con?guration the digital

data output transitions seen at the I/O header/connector are

essentially time aligned with the rising edge of the sampling

clock ( CLK ) or the falling edge of the out of phase sampling

clock (CLK).

Refer to the component layout and the evaluation board

electrical schematic for the following discussions.

SAMPLE

CLOCK

INPUT

50 ?

+5V D

BIAS

TEE

CLK

CLOCK

OUT

CLK

1.2V

BANDGAP

VOLTAGE

VAR

GAIN

+2.5V

CLK

V REFIN

REFERENCE

V REFOUT

ANALOG

INPUT

TRANSFORMER

V IN +

D 0 -D 9

DIGITAL

DATA

OUT

(D0 - D9)

V IN -

HI5767

DGND

AGND

+5V D

+5V A

-5V A

3-1

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Corporation.

? Intersil Corporation 2000

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式